The present invention relates to a COC (Chip On Chip) type semiconductor device in which two semiconductor chips, each including a semiconductor integrated circuit formed on the upper surface thereof, are attached together by flip chip bonding.
In recent years, various efforts have been made in the art to realize a lower cost, a smaller size and a higher performance (e.g., a higher speed, and a lower power consumption) for a semiconductor device including an integrated circuit. For example, a COC type semiconductor device has been proposed in the art, in which two semiconductor chips are attached together by flip chip bonding, the two semiconductor chips including LSIs of different functions or LSIs that are produced by different processes.
A conventional semiconductor device in which two semiconductor chips are attached together by flip chip bonding, and a method for manufacturing the same, will now be described.
FIG. 11A is a schematic diagram illustrating a semiconductor wafer having formed therein a plurality of semiconductor chip areas each of which is to be a semiconductor chip mounted on a conventional semiconductor device. FIG. 11B is a plan view illustrating the upper surface of the semiconductor wafer of FIG. 11A on an enlarged scale.
As illustrated in FIG. 11A and FIG. 11B, a plurality of semiconductor chip areas 2 are formed on a semiconductor wafer 1. The semiconductor chip areas 2 are partitioned from one another by a separation line 3, and a plurality of electrode pads 4 are formed in each of the semiconductor chip areas 2. The semiconductor chip areas 2 are cut off from one another along the separation line 3 into semiconductor chips that are each mounted on a conventional semiconductor device.
Each electrode pad 4 formed in a semiconductor chip area 2 is used as an external electrode pad for electrical connection to an external circuit in some cases, and as a probe pad for an electrical inspection of the semiconductor chip in other cases. Thus, each electrode pad functions both as an external electrode pad and as an inspection electrode pad. Note that only the electrode pads 4 are drawn in the semiconductor chip areas 2 in FIG. 11B, and other wires, etc., are not shown in the figure.
FIG. 12A is a schematic diagram illustrating a semiconductor chip 2a that has been cut out from the semiconductor wafer 1 and another semiconductor chip 5, which are to be provided in a conventional semiconductor device, and FIG. 12B is a cross-sectional view illustrating the conventional semiconductor device.
As illustrated in FIG. 12A and FIG. 12B, a bump electrode 6 formed on an electrode pad 8 and an external electrode pad 7 are formed on the upper surface of the semiconductor chip 5. Moreover, a bump electrode 9 is formed on an electrode pad 4 on the upper surface of the semiconductor chip 2a. In a conventional semiconductor device 200, the semiconductor chip 5 and the semiconductor chip 2a are attached together by flip chip bonding, with the bump electrode 6 and the bump electrode 9 being connected together. As illustrated in FIG. 12A, the semiconductor chip 2a is mounted on an area of the upper surface of the semiconductor chip 5 that is indicated by a broken line.
In the conventional semiconductor device 200, the space between the semiconductor chip 5 and the semiconductor chip 2a is filled with an insulative resin 10, as illustrated in FIG. 12B. Moreover, the semiconductor chip 5 is fixed on a die pad 11 of a lead frame. Furthermore, the external electrode pad 7 of the semiconductor chip 5 and an inner lead 12 of the lead frame are electrically connected to each other by a thin metal wire 13. The semiconductor chip 5, the semiconductor chip 2a, the die pad 11, the inner lead 12 and the thin metal wire 13 are encapsulated by an encapsulation resin 14.
Next, a method for manufacturing the conventional semiconductor device 200 will be described.
First, an insulative resin is applied on a central portion of the upper surface of the semiconductor chip 5. Then, the semiconductor chip 2a is pressed against the semiconductor chip 5, and the bump electrode 6 of the semiconductor chip 5 is connected to the bump electrode 9 of the semiconductor chip 2a. Note that the insulative resin may alternatively be injected into the space between the semiconductor chip 5 and the semiconductor chip 2a after they are connected together by flip chip bonding.
Then, after the external electrode pad 7 of the semiconductor chip 5 and the inner lead 12 of the lead frame are connected to each other by the thin metal wire 13, the semiconductor chip 2a, the semiconductor chip 5, the die pad 11, the inner lead 12 and the thin metal wire 13 are encapsulated by the encapsulation resin 14. Then, an outer lead of the lead frame protruding from the encapsulation resin 14 is shaped, thereby obtaining the semiconductor device 200.
However, with the conventional semiconductor device 200, the external electrode pad 7 to which the thin metal wire 13 is connected needs to be provided along the periphery of the semiconductor chip 5. In addition, the position at which the external electrode pad 7 is provided needs to be outside an area S on which the semiconductor chip 2a is to be mounted, as illustrated in FIG. 12A. Thus, the size of the semiconductor chip 5 needs to be larger than the size of the semiconductor chip 2a. 
A possible way to reduce the size of the semiconductor device is to reduce the size of the semiconductor chip 2a and thus the size of the semiconductor chip 5. However, it is difficult to reduce the size of the semiconductor chip 2a for the following reason.
The semiconductor chip areas 2 formed on the semiconductor wafer 1 are electrically inspected by a probing process, and only non-defective semiconductor chip areas are picked up. Then, those semiconductor chip areas 2 that have been picked up are separated, thereby obtaining semiconductor chips 2a, each of which is attached to the semiconductor chip 5 by flip chip bonding.
A probe pad is required in order to perform an electrical inspection by a probing process, and some of the electrode pads 4 in each semiconductor chip area 2 (semiconductor chip 2a) are probe pads. A probe may slide after contacting the electrode pad 4 being a probe pad. Therefore, in order to ensure that the probe contacts the electrode pad 4 being a probe pad, the electrode pad 4 being a probe pad needs to be formed with a size larger than a square of 70 xcexcmxc3x9770 xcexcm. This necessarily increases the size of the semiconductor chip 2a. Thus, it is difficult to reduce the size of the semiconductor chip 2a. 
Moreover, as semiconductor devices are provided with a higher performance (e.g., a higher speed, and a lower power consumption), the formation of a probe pad in the semiconductor chip area 2 (semiconductor chip 2a) makes non-negligible the influence of the capacitance, the inductance, etc., of each of the probe pad, the electrode pad, the protection circuit for the electrode pad, the bump electrode and the wire.
The present invention has been made to solve the problem in the prior art, and has an object to provide a semiconductor device having a small size and a high performance.
A semiconductor wafer of the present invention includes: a plurality of semiconductor chip areas each of which is to be a semiconductor chip; and a cut-off area for separating the plurality of semiconductor chip areas from one another so as to obtain the semiconductor chips, wherein: an integrated circuit and an electrode pad connected to the integrated circuit are provided in each of the semiconductor chip areas; and a probe pad connected to the electrode pad is provided in the cut-off area.
With the semiconductor wafer of the present invention, the semiconductor wafer is inspected by contacting a probe to the probe pad, after which the cut-off area having the probe pad, which is no longer needed after the inspection, is cut off and removed. Thus, the size of the semiconductor chip area to be the semiconductor chip is reduced. Therefore, according to the present invention, it is possible to obtain a semiconductor chip that is smaller than a semiconductor chip obtained from a conventional semiconductor wafer. Moreover, since the probe pad has been cut off and removed in the obtained semiconductor chip, it is not necessary to take into consideration the capacitance and the inductance of the probe pad. Therefore, the capacitance and the inductance of wires such as the electrode pad of the semiconductor chip of the present invention are smaller than those of the conventional semiconductor chip.
The number of electrode pads formed in each of the semiconductor chip areas may be larger than the number of probe pads connected to the electrode pads.
It is preferred that a pitch of the electrode pads formed in each of the semiconductor chip areas is smaller than a pitch of the probe pads connected to the electrode pads.
In this way, the shape of the probe pad can be elongated in the direction in which the probe is slid on the probe pad during the inspection. Thus, the inspection can be more reliable.
A size of the electrode pad formed in each of the semiconductor chip areas may be smaller than a size of the probe pad connected to the electrode pad.
The probe pads connected to the electrode pads may be formed along one, two or three sides of each of the semiconductor chip area.
A protection circuit for the probe pad may be provided in the cut-off area.
It is preferred that a wire connected to the electrode pad formed in each of the semiconductor chip areas is formed in a wiring layer that is below a wiring layer in which a wire connected to the probe pad is formed.
In this way, the wiring length from the internal circuit to the electrode pad can be reduced. Thus, the line capacitance can be reduced.
A semiconductor device of the present invention includes: a first semiconductor chip including a first integrated circuit, a first electrode pad connected to the first integrated circuit, and a first bump electrode formed on the first electrode pad; a second semiconductor chip including a second integrated circuit, a second electrode pad connected to the second integrated circuit, and a second bump electrode formed on the second electrode pad, wherein: a section of an inspection wire connected to the first electrode pad is exposed on a side surface of the first semiconductor chip; and the first bump electrode and the second bump electrode are electrically connected to each other.
With the semiconductor device of the present invention, the inspection wire, which is no longer needed after the inspection, is cut off and removed, and the area in which the inspection wire is provided is also removed. Thus, the size of the first semiconductor chip is smaller than that of a conventional semiconductor chip. Therefore, it is possible to obtain a semiconductor device that is smaller than a conventional semiconductor device. Moreover, since the inspection wire is cut off and removed from the first semiconductor chip, it is not necessary to take into consideration the capacitance and the inductance of the inspection wire. Therefore, the capacitance and the inductance of wires such as the electrode pad of the semiconductor device of the present invention are smaller than those of the conventional semiconductor device.
In the semiconductor device of the present invention, a probe pad may not be provided in the first semiconductor chip.
An external electrode pad for connection to an external circuit may be formed along a periphery of the second semiconductor chip.
An insulative resin may be provided between the first semiconductor chip and the second semiconductor chip.
The first semiconductor chip and the second semiconductor chip may be encapsulated by an encapsulation resin.
A method for manufacturing a semiconductor device of the present invention includes the steps of: (a) preparing a first semiconductor wafer, the first semiconductor wafer including: a plurality of first semiconductor chip areas each of which is to be a first semiconductor chip; and a cut-off area for separating the plurality of first semiconductor chip areas from one another so as to obtain the first semiconductor chips, wherein: a first integrated circuit and a first electrode pad connected to the first integrated circuit are provided in each of the first semiconductor chip areas; and a probe pad connected to the first electrode pad is provided in the cut-off area; (b) inspecting each of the first semiconductor chips by contacting a probe to the probe pad; (c) forming a first bump electrode on the first electrode pad; (d) removing the cut-off area of the first semiconductor wafer so as to obtain the first semiconductor chips from the first semiconductor chip areas; (e) preparing a second semiconductor wafer, the second semiconductor wafer including a plurality of second semiconductor chip areas each of which includes a second integrated circuit, and a second electrode pad connected to the second integrated circuit, and each of which is to be a second semiconductor chip; (f) forming a second bump electrode on the second electrode pad formed in each of the second semiconductor chip areas; (g) heating and pressing the first bump electrode and the second bump electrode against each other so as to electrically connect the first bump electrode and the second bump electrode to each other; and (h) cutting the second semiconductor wafer so as to separate the second semiconductor chip areas from one another.
With the method of the present invention, the probe pad, which is no longer needed after the inspection, is cut off and removed from the first semiconductor chip. Thus, the size of the first semiconductor chip is smaller than that of a conventional semiconductor chip. Therefore, it is possible to obtain a semiconductor device that is smaller than a conventional semiconductor device. Moreover, since the probe pad is cut off and removed from the first semiconductor chip, it is not necessary to take into consideration the capacitance and the inductance of the probe pad in the obtained semiconductor device. Therefore, according to the present invention, it is possible to obtain a semiconductor device in which the capacitance and the inductance of wires such as the electrode pad are smaller than those of the conventional semiconductor device.
In the step (g), an insulative resin may be supplied between the first semiconductor chip and the second semiconductor chip.
In the step (c) and the step (f), the first bump electrode and the second bump electrode may be formed by using one of an electroplating method, an electroless plating method, a printing method, a dipping method, and a stud bump method.
In the step (c), the first bump electrode may be made of one of an alloy containing tin and silver, an alloy containing tin and lead, tin, nickel, copper, indium, and gold.